Digital computer apparatus



s. A. BoRbELoN, 'JR 3,121,787

DIGITAL COMPUTER APPARATUS 2 SheetsSheet 1 Feb. 1s', 1964v Flled Dec.12, 1960 Feb. 18, 1964 S. A. BCRDELON, JR

DIGITAL COMPUTER APPARATUS 2 Sheets-Sheet 2 Filed Dec. 12, 1960 QQ .QQ

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United States Patent O 3,121,787 DGITAL CUMPUTER APPARATUS Sidney A.Bordelon, fir., Anaheim, Calif., assignor to Hughes Aircraft Company,Culver City, Calif., a corporation ol Delaware Filed Dec. 12, 1960, Ser.No. 75,443 1 Claim. (lll.l 23d-92) This invention relates to a digitalcomputer counting apparatus and, more particularly, to a high-speeddigital computer counting apparatus exceeding 12 bits and incorporatingnovel xfast-acting carry propagation Igates.

ln conventional binary counter apparatuses, the inputs of thoseflip-flops incorporated therein which correspond to the moresignifican-t `digits are dependent upon outputs from all the flip-flopscorresponding to the less sigiiicant digits. There are two principalWays to implement this type or" counter. ln -a lirst Way, each flip-iopof the counter is designed to be capable of driving all succeedingdip-flops corresponding to the more siguicant digits. Thus, in a llt-bitcounter, the iiip-ilop corresponding to the least significant digitAmust be capable of driving all of the succeeding i3 {lip-flops. In thecase of most general iiip-ilops, this capability is very unlikely inthat a typical general purpose flip-liep can under normal conditionsdrive only 6 ilip-tlops or l2 NR gates.

A second possibility is to employ NOR ga es to regenerate the moreheavily loaded iliplop output signals. Two alternatives are possiblewhen employing NR gates for this purpose. One alternative is to minimizetota delay which the NOR gates introduce during regeneration, and theother alternative is to minimize the total number or" NOR gates neededto provide the minimum amount of regeneration. ln general, .it issufficient to say that the imo-wn techniques employed to minimize delayall require a large number or NOR gates. Gn the other hand, when atechnique to minimize the number of NOR gates is employed, intolerabledelay result.

To understand more clearly the eiiects of the aforementioned delay,consider a long binary counter such as a lll-bit counter. The timerequired for this counter to prepare itself for a change from all ls toall Os when counting up (or the opposite when counting down) isproportional to the number of bits in the counter when the number of NORgates used is minimized. This limitation must be applied to allsucceeding iiip-ilops in the counter. For example, in the case of theiiip-ilop corresponding to the tlurd least significant digit in theaforementioned l4-bit counter, the load under these circumstances inaddition to loading external to the counter will be the inputs tothesucceeding 11 flip-flops. 'lhe location of regeneration elements such asNOR gates in series lwith the third least signiicant ilip- Lop outputintroduces a time delay in the arrival of the carry signal at the mostsignin-cant digit flip-tldp input. Hence, as the counter is made longer,the number of series regeneration ele-ments in eases thus lfurtherincreasing the time delay. The significance ci the delay is that ytheclock pulse spacing can be no closer thm the slr/itching time of ailip-ilop in the least significant :digi-t position plus the total delaytime for that output to reach and set up the hip-flop corresponding tothe most significant digit. If, for example, standard NOR gates andgeneral purpose ilip-llops are used to mechanize the aforementionedcounter, the logic designer is faced with two problems; first, theminimization of the total number of NOR gates used and, secondly, theminimization of tot-al signal propagation time between iiip-lcpscorresponding to the least siguiiicant digit and the most significantdigit.

lt is therefore and object oi the present invention to provide animproved digital computer counting apparatus.

3,l2l,787 Patented Feb. 18, 1964 ICC Another object of the presentinvention is t0 provide a long count-up, count-down counter having a-minimum total number of gates.

Still another object of the present invention is to provide a digitalcomputer counting apparatus incorporating carry propagation gates whichsubstantially reduce the delay between ilip-liops corresponding lto theleast signicant digit and the moist significant digit over thatobtainable with conventional gating methods. n

A further object of the present invent-ion is to provide an improvedcarry propagation gate for use in digital computing apparatus.

ln the iol-lowing description, the binary counter of the presentinvention is considered as being a one-bit-time, parallel, add-onebinary adder. In accordance with the invention, however, the adderincorporates an improved carry propagation Vgate between every flip-flopconstituting the storage register of the counter. Each of theaforementioned carry propagation gates perform logic delined as follows:

wherein a bar over a quantity designates the negation or complement ofthat quantity, and the and the indicate the Boolean logic OR and ANDfunctions, respectively. ln particular, CN designates the carry digitfrom the (N-l)th digit of the binary number; U designates the signal torcounting up, D designates the signal for counting dowrg and QN and (5Ndesignate the principal and complementary outputs, respectively, of thedip-flop corresponding to the Nth digit of the binary number stored inthe counter. Relations (l) and (2) designate that the output, N, oi aparticular carry propagation gate is the same 'as the input carrysignal, N `1, provided that (QN 1U) or (N 1D) are at the informationlevel. lt is thus `apparent that the binary counter of the presentinvention is of a type wherein the rate at which a carry signal ispropagated along the length of the register is not dependent uponsuccessive changes in the state of successive flip-flops but rather uponthe rate at which the successive carry propagation igates are capableor" changing state.

ln 4the device of the present invention, all flip-flops that are goingto change state in response to -a particular pulse to be counted makethis change simultaneously in respouse to a clock pulse, .which can bethe pulse being counted. Accordingly, the Worst case for time delayoccurs when the outputs or" the flip-flop corresponding to the leastsignificant digit must travel the electrical length of the counter tothe inputs of the ilip-tiop correspondinf.y the most significant digit,land in so doing set up all the ilip-ops in the counter so that theywill each change state at the next clock time. During the birt intervalimmediately prior to the clock time When the principal output from allthe ilip-llops will change from the information level to the zero levelin the vcount-up procedure, (QN 1'U) is in each case at the informationlevel with the exception of (Q1-U), which quantity changes dromthe zerolevel to the information level during this interval, and, in `so doing,initiates a carry signal propagation which sets up the remainingilipdlops. It is apparent from relation (1) that the output of eachcarry propagation gate will be the same as the output of 'the precedingcarry propagation gate, and that no other iiipllop need change stateduring this interval. The respective carry propagation gates need onlysense the state of -the corresponding dip-flops and transpose the carrysignal from the inputs to the outputs thereof with minimum delay. lnparticular, the carry propagation gate;I

of the present invention incorporate emitter-follower type circuitrythat is adapted to transpose and regenerate carry signals withoutinversion at extremely fast rates compared with conventional techniques,thereby making possible the implementation of long digital binarycounters with a minimum of both gating and delay simultaneously.

rIlhe above-mentioned and other features and objects of this inventionand the manner of obtaining them will become more apparent by referenceto the following description taken in conjunction with the accompanyingdrawings, wherein:

FIG. l is a schematic block diagram of a binary counter in accordancewith the present invention; and

FIG. 2 illustrates a schematic circuit diagram of one of the carrypropagation gates in 'the apparatus of FIG. l.

In describing 4the apparatus of the present invention, a convention isemployed wherein individual AND gates are shown as seniieircular blockswith the inputs applied to the straight side and the output appearing onthe semicircular side. An AND gate is indicated by a dot in thesemi-circular block. As is generally lznown, an AND gate produces a oneor information level output signal only when every input is at theinformation level; i.e., the output signal is the conjunction of theinput signals.

In addition to the above, a convention is employed wherein individualNOR gates are shown as isosceles trapezoids with the inputs applied tothe longer side, and the output appearing on the shorter side. A NORgate is indicated by a disposed within `the isoseeles trapezoidalblocks. As is 'generally known, a NOR gate produces a signalrepresentative of the conjunction of the negations or complements of therespective input signals or, expressed differently, the ynegation orcomplement of the alternations of the input signals.

A further convention is employed in describing the particularembodiments of the present invention wherein leads to the upper andlower portion of the left side of the respective rectangles representinghip-flops, as they appear inthe drawings, are designated as the set andreset inputs, respectively. Further, the principal and complementaryoutput terminals from the iiip-op emanate from the upper and lowerportion of the right side of the rectangie, respectivcly. An informationlevel signal applied to either the set or reset input of a liip-op willresult in a possible change of state thereof at the next clock time if azero level signal is applied to the remaining input, whereby aninformation level signal appears at the corresponding principal orcomplementary output terminal. Lastly, it is considered within thepresent state of the computer art that Hip-flops may be employed whichpossess an AND gate at its set and reset inputs, which AND gate is anintegral part of its circuit.

Referring now more particularly to FIG. 1, a preferred embodiment of thedigital computer counting apparatus of the present invention iscomprised of a plurality of ip-tlops or counter stages r11, 12, 13, 14and 15, corresponding, respectively, to stages PF1, FP2, FF3, FFM 1 andFFM, wherein M is the total number of stages in the register of thecounter. The total number of tlip-ops to be employed will be determinedby the number of signal pulses to be counted. Each of the flip-flops 1-1through 15 possesses a set input designated by S, and a reset inputdesignated by R. Also, the ilip-iiops 11 through 15 each generate twostable states which are evidenced by complementary Ivoltage waveformswhich appear at the principal and complementary outputs and aredesignated as QN and N, respectively, N being any of the flip-flops from1 to M. In order for the flip-flops to change state, an informationlevel signal is 4applied at either of the set or reset inputs and a zerolevel signal is applied to the remaining input. In the event aninformation level signal is applied to the set input, the tlip-ilop willassume or maintain the state wherein an information level signal isgenerated at the principal output commencing with the next succeedingclock time. On the other hand, if an information ievel signal is appliedto the reset input, the ip-op will assume or maintain the state whereinan information level signal is generated at the complementary Outputcommencing with the next succeeding clock time.

A succession of pulse type input signals to be counted is provided by apulse source 10. These pulse type input signals are applied throughinput terminal 16 to an input of a two-input AND gate 18 along withclock pulse signals applied over a lead 19 from a clock pulse generator26. The output of the AND gate 18 is applied in parallel to the clockpulse input of each of the flip-flops 11 through `15. The clock pulsesthus applied to each of the iiip-ops 11 through 15 are ANDed with thesignals appearing at the set and reset inputs. Hence, if no informationlevel signals appears on the set or reset inputs, the iptop will notchange state; if an information level signal :is applied `to the setinput, the flip-flop will assume or maintain the state wherein aninformation level signal is generated on `the principal output at thenext clock time; and if an information level signal is applied to therreset input, the flip-iop will assume or maintain the state wherein aninformation level signal is generated on the complementary outputthereof. The principal outputs of the flip-flops 11 through 15 areconnected to output terminals 22, 23, 2d, 2S and 26, respectively, toprovide a parallel output from the disclosed counter. The set input ofthe flip-flop `11 is connected to the output of a single input NOR gate27, and the reset input connected to the output of a similar singleinput NOR gate 28. In addition, the principal output of flip-flop 11 isconnected to the input of NOR gate 27, and the complementary outputthereof is connected to the input of the NOR gate 28. In that the NORgates 27 and 28 have only a single input, it is evident that theyfunction as inverters. Thus, in effect, the complementary outputwaveform Q1 is aplied to 'the set input, and the principal outputwaveform Q1 is applied to the reset input of liip-op 11. This being thecase, it is apparent that Hip-flop 11 will change state in response toevery clock pulse generated at the output of AND gate 18.

The set input of dip-flop 12 is connected to the output of a two-inputNOR gate 30, and the reset input is connected to the output of atwo-input NOR gate 31. In a manner similar -to the llip-op 11, theprincipal output of flip-flop 12 is connected to an input of the NORgate 30, and the complementary output of flip-Hop 12 is connected to `aninput of the NOR gate 31. The remaining inputs of the NOR gates 30 and31 both receive a carry signal in a manner hereinafter described.Similarly, the set inputs of flip-iiops 13, 14 and 15 are connected tothe respective outputs of two-input NOR gates 33, 34 and 35,respectively, and the reset inputs connected to the outputs of two-inputNOR gates 36, 37 and 38, respectively. The principal outputs offlip-flops 13, 14 and 15 are applied, respectively, to an input of theNOR gates 33, 34, and 35', and the complementary outputs thereof to aninput of the NOR gates 36, 37 and 33.

The remaining inputs of the NOR gates 30, 3l; 33, 36; 34, 37; and 35, 38receive carry signals from carry propa- -gation gates 39, 4t), 41 and42, respectively.

Each of the carry propagation gates 39, 40, 41 and 42 generate thelogical output:

in response to AN, BN and N 1 inputs. In the aforementioned relationship(3), N assumes successive values from 2 to M, and 1 is ldefined asalways being equal to zero. That is, C1 is always equal to unity so asto increase or decrease the count stored in the ip-ops by one at everyclock time. A more detailed description of the operation of carrypropagation gates 39, 4t), 41 and 42 is presented in connection with thedescription ot FlG. 2 ot the drawings. The respective outputs oftwoinput NOR ygates 44, 45, 46 and 47 are applied to the AN inputs ofcarry propagation gates 39, 4t), il and 42, respectively, and therespective outputs of two-input NOR gates 4S, 49, Sil `and 5l areapplied to the BN inputs of carry propagation gates 39, 40, 41 and 42,respectively. ln accordance with the aforementioned definition, n1always equals zero whereby a zero level signal is applied to the N 1input of carry propagation gate 3? by means of a connection therefrom toground over la lead 53. The output ott carry propagation gate 39 is thenapplied in parallel to the inputs of NOR gates 3@ and 3l as Well as tothe U2 input of carry propagation l ate 4i?. Likewise, the output otcarry propagation gate t9 is applied to the inputs of NOR gates 33 `and36 as well as to the 61(1 2 input of carry propagation gate all. Theoutput of carry propagation gate l1 is, in turn, applied to inputs ofNOR gates 34 and 37 as well as to the -C Mml input of carry propagationgate 42. Lastly, the output of carry propagation gate 42 whichconstitutes 'the carry signal M is applied to inputs of NOR gates 35`and 38.

An undown liip-ilop '54 is provided for controlling whether thedisclosed counting apparatus counts up or down. Accordingly, theprincipal and complementary output signals generated by flip-liep 54 aredesignated U and D, respectively. ln that the signals U and D are alwayscomplementary, the signal U may also be designated as and the signal Das The signal -available at the complementary output of Hip-flop 54 isapplied to an input of each of the NOR gates 4d, 45, 416 and d'7, andthe signal l5 available at the principal output of llip-flop 5d isapplied to an input or each of the NOP. gates 48, 49, Sil and 5l. 'Inaddition, the signals Q1 through QM 1 available at the principal outputs`of Jflip-flops il through 14 are applied, respectively, to theremaining inputs of OR gates i3 through Si `and the signals 1 throughQ'egl available at the complementary outputs of flip-flops :11 throughElfi are applied to the remaining inputs of NOi?` gates through 47,respectively.

The operation of the apparatus of FIG. 1 can best be demonstrated byshowing that the logic of the signals appearing at the respective S andl inputs of the iipdlops lll through is conventional. As is evident fromHG. 1 of the drawings,

Also, the signals N and QN are applied through the r e spective NORgates lto SN of FFN and the signals CN and N are applied through therespective NOR gates to RN of PPN whereoy As previously speciiied, Ncommences at 2 and C1 is delined as always being equal to unity. Thusfor N less than or equal to M, relations (11) and (12) become:

clock pulses generated Iat the output of AND gate i8 up or downdependent upon which of the complementary control signals U or D is atthe infomation level.

Referring now to PEG. 2 ort the drawings, there is shown a schematiccircuit diagram of the carry propaga- `tion gates 39, ttl, il yor 42.Each of the carry propagatic-n gates 39, 4u, il or i2 are comprised ofan n-p-n type transistor 60, having a base 6l, a collector 52 and anemitter 53, and a p-n-p type ytransistor having a base 66, a collector67 and an emitter 68, the emitter 68 of transistor 65' being connected`directly to the emitter 63 of transistor ed. 'lhe base 6l ot transistor60 is connected through a high conductance type germanium diode 70 toground, which diode 7i) is pole-d to allow cur rent to flow towardsground. In addition, base 66 of transistor 65 is connected through aquick recovery type silicon diode 7l to groruid, diode '71 `being poledto allow current liow away from ground. The base 66 of transistor SS isfurther connected through a resistor 72 to a junction 73 which, in turn,is connected through a diode 7d to an input terminal 75, previouslydesignated the AN input, land through a diode '76 to an input terminal7?, previously designated as the BN input. The diodes 'i' and '76 areboth poled to allow current to flow away from the junction '73. Thecollector 67 of transistor di?, on the other hand, is connected toanoutput terminal 8% which, in turn, is connected to the inputs of NORgates 3i), El; 33, 36; 3d, 37; or 35, 3S, which amounts to a loadimpedance of the order of 5006 chains.

Voltage for the transistors all and 65 is provided, by way of example,by a battery S2 having an intermediate terminal thereof connected toground, an intermediate positive terminal capable of developing of theorder of +15 volts relative to ground connected to Ithe collector e2 oftransistor all and a positive terminal S3 capable of developing +15volts relative to ground connected through a resistor tidto the base 6eof transistor 65. ln addition to the foregoing, battery S2 has anegative terminal S25 capable of developing -15 Volts relative toground. An input terminal 91 ot carry propagation gates el?, il and ft2is connected to the output terminal d@ ot the preceding carrypropagation gates 39, lil and el, respectively, and the input terminal9'1 of carry propagation gate .'59 is connected to ground. Seriallyconnes d resistors S7 and 88 are connected in the order from thepositive terminal ii?? to the Vinput terminal 9i which, in turn, isconnected to the preceding output ten rninal 853' which is returnedthrough a resistor 89 to the negative terminal 8S of battery 82, wherebyresistors 37, 33 and constitute a resstor-didinig network across thebattery 82. Resistor 83 of this network is shunted by a capacitor 99;,and the junction between resist-ors il? and S8 is `connected to the haseel of transistor 6?.

During the operatic-n of the disclosed apparatus of the presentinvention, a zero level signal is deiined as ground or zero volt, and aninformation level signal is defined as a negative poter ial or" theorder of -6 volts relative to ground. rEhe logical requirement of thecarry propagation gates 39, 4G, il or 42 as specified in relation (3)may be expressed as ltoll-owls:

The apparatus of FIG. 2 must perform the logic or" relation 15) for allcombinations of N 1, N, and EN which are considered in the followingcases I, Il and lll.

Case 1.-Assume AN=BN=O whereby -N and EN are both at information level.With these inputs, the logic of relation (l) dictates that N must be atinformation level irrespective of whether N 1 is at zero or informationlevel. Referring now to FIG. 2, the germanium diode 7l) prevents `theresistor-dividing network formed by resistors 87, 8S and S9 from raisingthe potential applied to base 61 of transistor 60 to more than +0.4 voltwith respect to ground. Next, the input terminals 75 and 77 are bothmaintained at zero volt, i.e., AN=BN=O, whereby resistors 84 and 72, anddiodes 74 and 7 6 form a potential dividing network with the resul-tbeing that a potential more positive than +0.5 volt lrelative to groundis applied to the oase 66 of transistor 65, thus back-bias-` ing thediode 71. Since lthe base 66 of transistor 65 is now more positive thanthe base 61 of transistor 60, current flow through both of thetransistors 6i? and 65 is cut off. Under the foregoing circumstance, itis immaterial whether or not the base 61 is more negative than the +0.4Volt; hence, both possibilities for N 1, i.e., zero volt or -6 volts atinput terminal 91, are covered. With current flow cut off, the outputterminal 80 is pulled negative by reduced current flow to the negativeterminal S5 of battery 82 through resistor 39, thereby generating aninformation level output signal.

Case II.-Assume that AN or BN or both are at the information level,whereby NN of relation (15) is at zero level, and N 1 is at theinfomation level. Under these circumstances N must equal N 1 which is atthe information level. Referring to FIG. 2, the application of aninformation level signal to either input terminal 75 or 77 results inback-biasing the opposite diode 76 or 74, respectively, wherebyresistors 84 and 72 form a resistordividing network from the voltsavailable at the positive terminal S3 of battery 82 to the potential ofthe information level signal AN or BN which is -6 volts relative toground. This action, however, is limited at the base 66 of transistor 65by the silicon diode 71, which prevents the base from going morenegative than 0.8 volt relative to ground. On the other hand, with aninformation level input, i.e., -6 volts, at input terminal 91, the base`til of transistor 60 is maintained at a potential of the order of 1.6volts relative to ground, which is negative relative to the potential ofbase 66, thereby cutting off current flow through both transistors 60and 65. Consequently, the output termial Sti is maintained atinformation level (-6 volts) by reduced current flow through resistor 39to the negative terminal 85 of battery 82 in the same manner as in caseI. It is to be noted that the output terminal 80 is at the informationlevel which is the same as that of the applied signal, N 1.

Case IIL-Assume that AN or BN or obth are at the information level,whereby N-N of relation (l5) is at Zero level, and N 1 is `at zerolevel. As before N must equal N 1, but, unlike before, N 1 is now atzero level. Also, as in case Il, the application of an information levelsignal to either input terminal 75 or 77 results in back-biasing theopposite diode 76 or 74, respectively, whereby resistors 84 vand 72 forma resistordividing network from the +15 volts available at the positiveterminal 83 of battery 82 to the potential of the information levelsignal AN or BN which is -6 volts relative to ground. Unlike case ll,however, the zero level signal applied to input terminal 91 results in apotential of +0.4 volt relative to ground at the base 61 of transistor60, thus making the potential of base 61 positive relative to that o-fbase 66, whereby transistors 60 land 65 both conduct. The increasedcurrent due :to this conduction tends to increase the potential level atbase 56. This effect, together with the clamping effect of diode 71,results in a potential of 0.4 volt relative to ground at the base 66 oftransistor 65, which is still negative relative to the potential of base61 of transistor 60. The resistances of the resistors 37, S8 and 89 areselected so that under these circumstances :the voltage developed atoutput terminal is +0.05 volt relative to ground which is consideredzero level by definition and which is the same level as that of theapplied signal, N 1.

The function of capacitor is to provide transient base overdrive currentto transistor 60, thus increasing the speed of the emitter followeraction which this transistor provides. Also, the turn-olf transition oftransistor 60 is quickened considerably by returning the collector 62 tothe arbitrary, small positive voltage of the order of +15 volts. Thus,transistor 60 which generally nec not be an exceptionally high frequencytransistor will not saturate, `whereby rthe effective frequency responseis increased. Since transistor 65, on the other hand, must go intosaturation, it is desirable to employ a high frequency transistor forthis component. Examples of parameter values for the elements of carrypropagation gates 39, 40, 41 or 42 which may be employed to achieve theresults described above are as follows:

Transistor 6i) 2N383 Transistor 65 2Nl500 Diode 7@ HD2552 Diode 71 1N626Diodes 74, 76 HD6379 Resistor 72 ohms 4,640 Resistor 84 -do- 31,600Resistor 87 do- 38,300 Resistor 88 do 8,250 Resistor 89 do 4,220Capacitor 9a? -micromicrofarads 220 The above values of resistance arebased upon an additional load impedance of the order of 5000 ohms beingconnected between the output terminal 80 and ground potential. In theapparatus of FiG. 1, this additional load impedance has the form of theparallel NOR gates 30, 31; 33, 36; 34, 37; or 35, 38. With theaboveidentiied components and parameter values; it was determined that a"0 or l propagated through 1l carry propagation gates of Ithe presentinvention in less than 0.6 microsecond, and the delay between the AN orBN inputs and the N output of the same switch is less than 0.4microseconds.

Although the invention has been shown in connection with a certainspecific embodiment, it will be readily apparent `to those skilled inthe art that various changes in form and arrangement of parts may bemade to suit requirements without departing from the spirit and scope ofthe invention.

What is claimed is:

A digital computer apparatus comprising means including a plurality ofbistable elements for providing storage for a binary number, each ofsaid bistable elements having a set and a reset input for controllingthe level of the potential developed at principal and complementaryoutputs, respectively; means for developing complementary bi-levclsignals U and D for controlling whether said apparatus counts up ordown, respectively, in response to pulse signals to be counted; carrypropagation means interconnected between each successive pair of saidbistable elements, thereby forming a sequence of said carry propagationmeans for producing successive signals representative of the logicCN+1=CN+(QN+U)+(QN+) wherein N is a positive integer which assumessuccessive values commencing from no less than one, N and NH are thenegations of the carry signals, which negations thereof are developed bythe (N-l)st and the Nth carry propagation means, respectively, of saidsequence thereof, l of which is delined as always being at zero level,and

QN and N are the principal and `complementary output signals,respectively, developed by the Nth bistable element corresponding to theNth digit of said binary number; and a gating means corresponding toeach respective bistable element, each gating means being responsivedirectly to pulse signals to be counted, to voltages available atprincipal and complementary outputs of the respective correspondingbistable element, and to respective carry signals for controlling theapplication of information level signals ,to respective set and resetinputs of said lbistable elements thereby to change 'the value olf saidbinary number by one upon the occurrence of each of said pulse signals'to be counted.

References Cited in the file of this patent UNITED STATES PATENTS2,735,005 Steele Feb. 14, 1956 2,764,343 Diener Sept. 26, 19562,819,840y Huntley et al lan. 14, 1958 2,844,317 Shillington July 22,1958 2,848,166 Wagner Aug. 19, 1958 2,941,721 Schaft et al. June 2l,1960 2,953,695 Rywak Sept. 20, I196() 2,986,655 Wiseman et al May 30,1961 3,022,945 Carroll et al. Feb. 27, 1962 3,023,371 Balisll et al. Feb27, 1962 3,051,848 Clark Au-g. 28, 1962 3,059,226 Einsele Oct. 16, 1962OTHER REFERENCES A Formal Procedure for the Logical Design of an OptimumBinary Counter, by Cohen, from Proc of the Natl. Electronics Conference,1954, pp. 523-532.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,l2l787 February 18Y 1964 Sidney A Bordelon, Jro

It is hereby certified that error appears in the above numbered patentrequiring correction and that the said Letters Patent should read ascorrected below.

Column 5, lines 66 and 67, the relations should appear as shown belowinstead of as in the patent:

Column 61l lines 6 and 7v the upper portion of relation "(14) shouldappear as shown below instead of as in the patent:

column 7, line I9y for "termial" read terminal line 55 for "obth" read-aboth Signed and sealed this 21st day of July v1964,

(SEAL) y Attest:

ESTON G., JOHNSON I EDWARD J BRENNER Atstesting Officer Commissioner ofPatents

